Modeling dispersion of partial discharges due to propagation velocity variation in power cables

Existing models for partial discharge (PD) propagation based on a single attenuation constant are unable to explain how each frequency component travels with a different propagation velocity. This paper proposes a new model based on a complex propagation term whose real component does not depend on the frequency ($f$), and whose imaginary part is modeled with a second order polynomial in $f$. The proposed model explains how the PD is attenuated, delayed, and dispersed due to the fact that each frequency component is differently delayed. A closed-form expression is proposed for the PD peak value and width, and a method to derive the model parameters from a reference model existing in the bibliography. Simulation results show that the peak value and width of the propagated PD pulse are similar to those obtained with the proposed model. Additionally, the proposed model provides the velocity of each PD frequency component, which is crucial to get an accurate estimation of the PD source location. The parameters of the proposed model have been estimated using a vector network analyzer for a XLPE cable. These results have been compared to the measurement obtained in a medium voltage test bench where intentionally induced PDs have been captured and processed, confirming the results of attenuation, delay and dispersion predicted by the proposed model

Three methods for the parallel solution of a large, sparse system of linear equations by multiprocessors

In this paper three methods for the parallel solution of large-scale, sparse, linear equation systems are presented and compared. Both, factorization of the matrix and forward backward. Processes have been considered. A multiprocessor architecture has been simulated and results are presented corresponding to eight examples taken from power systems field, ranging from 117 to 660 equations

Implementación de un controlador borroso usando técnicas de PWM analógico

Hoy día la mayoría de los sistemas de control borroso se implementan en software usando procesadores y micro controladores digitales. Los diseños digitales programables son capaces de resolver muchos problemas de control, pero en sistemas de tiempo real, donde las señales de control tienen que cambiar en solo unos ciclos del reloj, la implementación hardware es la única solución posible. En este artículo se presenta un diseño de VLSI hardware, basado en técnicas de diseño analógicas usando trenes de pulsos. El diseño implementa todas las partes de un controlador borroso de alta velocidad. Se ha construido un chip de prueba en 1.5um CMOS

Red Neuronal de Hopfield con técnicas de procesamiento estocástico paralelo-secuencial

En este artículo se presenta la realización de una Red Nueronal Estocástica de Hopfield (SHNN) con un gran número de unidades. Originalmente, la SHNN propuesta por van de Bout, requiere tiempos de convergencia grandes al acumularse en el Estado neuronal los pulsos estocáticos que codifican las sinapsis secuenciamente. En otras realizaciones los pulsos sinápticos son acumulados en paralelo pero encuentran limitado el número máximo de neuronas de la red en arquitecturas multichip a 100 unidades aproximadamente. Este hecho se debe a las limitaciones que hoy por hoy la tecnología impone el número de pines de l/0 en los circuitos integrados. A continuación se propone una realización multichip que permite establecer un compromiso entre los problemas planteados anteriormente. La arquitectura, basada en la utilización de una estrategia mixta paralelo-secuencial reduce el número de líneas de Interconexi6n al valor de k y aumenta la velocidad de convergencia respecto al SHNN secuencial por un factor de k. Para evaluar el comportamiento de la red se ha simulado y resuelto un problema de partición

FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

Effects of Dispersion and Multi-Path Propagation in Partial Discharges Location

Article number 9281048Dispersion and multi-path propagation distort partial discharge (PD) pulses that travel along power cables. This article proposes a theoretical framework that models the PD source location error owing to these effects. Regarding dispersion a closed-form expression is proposed to estimate the PD bandwidth reduction at the cable ends as well as the expected location error due to propagation velocity variation. A new expression is proposed for the difference of times of arrival (TOAs) which exhibits dependence with frequency. Multi-path propagation also introduces a non-linear dependence with frequency in the TOAs which leads to location errors when the echo is very close to the main PD signal. Three location algorithms (based on cross-correlation phase increment and energy criterion) are investigated under noise dispersion and multi-path conditions. Simulation results show that the energy criterion algorithm is very sensitive to dispersion but it is robust to multi-path propagation. The algorithm based on phase increments is the most sensitive to noise. Finally the best location method for noisy highly dispersive multi-path propagation is the one based on cross-correlation.Laboratorio de Ingeniería en Energía y Sostenibilidad Ambiental de la Universidad de Sevilla VI Plan Propio de Investigació

Partial discharge detection using PLC receivers in MV cables: A theoretical framework

Partial discharge (PD) activity is a key indicator of the cable insulation health in medium-voltage networks. Many of these cables are used as transmission media, because power line communication (PLC) modems are installed at their ends. This paper proposes two techniques that allow broadband PLC receivers to detect PDs at the same time that the PLC signal is being demodulated. The proposed techniques are based on how PDs alter both, null, and zero-bit loaded carriers, commonly used in orthogonal frequency division multiplexing modems. Using the proposed techniques, a simple firmware modification is sufficient to add this new functionality to the already installed modems. This paper is mainly concerned with theoretical aspects of the proposed techniques, and no experimental validation has been done. Nevertheless, simulation results show that the proposed techniques can be used to detect different types of PDs. Four cases studies are analyzed: short- and long-distance PDs, and low- and high-energy PDs. Finally, the impact of the inter-carrier interference on the detection capability is studied, and some recommendations are made to mitigate its effects

Selección automática de topologías

Se presenta una herramienta para la selección de topologías a partir de unas especificaciones de entre un conjunto de topologías alternativas fijas empleando lógica borrosa. Las reglas de decisión empleadas pueden proceder del conocimiento de un diseñador experto o ser generadas automáticamente mediante un procedimiento de aprendizaje a partir de los resultados de la optimización de una rejilla de especificaciones. Se muestran una serie de ejemplos que reflejan la capacidad de la herramienta para aprender la elección de celdas analógicas

Aceleración de un algoritmo de enfriamiento simulado mediante particionamiento de redes. Aplicación a "placement" de circuitos VLSI

Se propone un nuevo método de mejora de los resultados del "placement" de un circuito VLSI. El método propuesto utiliza un particionamiento recursivo para obtener una solución de partida para el posterior proceso de enfriamiento simulado. Para preservar los beneficios de esta solución de partida, la temperatura inicial del algoritmo de enfriamiento es seleccionada del espacio intermedio de las temperaturas. Se presentan resultados experimentales sobre diversos circuitos de prueba, demostrando que el método propuesto mejora el coste final de un 5% respecto de los resultados del programa TimberWolfSC Ver. 6.1. Es más, el tiempo de computación requerido viene a ser alrededor de un 40% menor que el empleado por TimberWolfSC Ver . 6.1

A collection of fuzzy logic-based tools for the automated design, modelling and test of analog circuits

We have developed a collection of tools for the design, modeling, and test of analog circuits. Sharing a common fuzzy-logic based framework, the tools are part of FASY (Fuzzy-Logic-Based Analog Synthesis), an analog design package developed at the University of Seville. The first tool uses fuzzy logic for topology selection of analog cells. It follows decision rules directly entered by a human expert or automatically generated from its experience with earlier designs. Second, a performance-modeling tool provides a qualitative description of a circuit's behavior. Alternatively, it can use a learning process to accurately model circuit performance. Finally, an analog testing tool uses a fuzzy-neuron classifier to detect and classify faults in analog circuits